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Front End
InstructionCache Tag
µOP CacheTag
L1 Instruction Cache32KiB 8-Way
InstructionTLB
Instruction Fetch & PreDecode(16 B window)
Instruction Queue
MOP
MicroCodeSequencerROM(MS ROM)
Decoded Stream Buffer (DSB)(µOP Cache)(1.5k µOPs; 8-Way)(64 B window)
BranchPredictor(BPU)
Allocation Queue (IDQ) (128, 2x64 µOPs)
L2 Cache1 MiB 16-Way
Unified STLB
Execution Engine
Memory Subsystem
L1 Data Cache32KiB 8-Way
Data TLB
SchedulerUnified Reservation Station (RS)(97 entries)
Integer Physical Register File(180 Registers)
Vector Physical Register File(168 Registers)
Port 0
Port 1
Port 5
Port 6
Port 2
Port 3
Port 4
Port 7
INT ALU
INT DIV
INT Vect ALU
INT Vect MUL
FP FMA
AES
Vect String
FP DIV
INT ALU
INT MUL
INT Vect ALU
INT Vect MUL
FP FMA
Bit Scan
INT ALU
LEA
INT ALU
Branch
AGU
Load Data
AGU
Load Data
AGU
(56 entries)
Store Buffer & Forwarding
64B/cycle
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
(50, 2x25 entries)
16 Bytes/cycle
µOP
µOP
µOP
µOP
µOP
µOP
Macro-Fusion
MOP
MOP
MOP
MOP
MOP
MOP
MOP
MOP
MOP
MOP
Micro-Fusion
64B/cycle
64B/cycle
StackEngine(SE)
Adder
Adder
Adder
≤4 µOPs
µOP
µOP
µOP
ComplexDecoder
4-Way Decode
SimpleDecoder
SimpleDecoder
SimpleDecoder
≤4 µOPs
MUX
≤5 µOPs
Loop StreamDetector (LSD)
Register Alias Table (RAT)
4 µOP
Branch Order Buffer(BOB) (48-entry)
Rename / Allocate / Retirement
ReOrder Buffer (224 entries)
Zeroing Idioms
Move Elimination
Ones Idioms
Line Fill Buffers (LFB)(10 entries)
Store Data
64B/cycle
64B/cycle
512bit/cycle
Load Buffer(72 entries)
≤6 µOPs
EUs
µOP
µOP
µOP
µOP
µOP
µOP
µOP
µOP
Common Data Buses (CDBs)
Int
Int Vect
FP
Load
Store
Branch
To L3
64B/cycle
512b fused
INT Vect ALU
INT Vect MUL
FP FMA
512b