2022-10-28-talk-fwam/intro.tex

% vim: set foldmethod=marker foldmarker=<<<,>>>:

\section{Introduction}

\begin{frame} \frametitle{What is HPC?}{} %<<<

  \begin{columns}
    \column{0.43\textwidth}
      \only<4>{%
        How can we keep our methods/algorithms and codes relevant in the future?
      }
    \column{0.56\textwidth}
      \centering
      \resizebox{0.99\textwidth}{!}{\begin{tikzpicture} %<<<
        \draw[black!0] (-4.73,-5) rectangle (4.73,4);

        \only<1->{
        \draw[color=green, ultra thick, fill=green, opacity=0.3] (1.73,1) circle (3);
        \node[text width=3.2cm] at (3.0,1.5) {\LARGE Methods \& Algorithms};
        }

        \only<2->{
        \draw[color=blue, ultra thick, fill=blue, opacity=0.3] (0,-2) circle (3);
        \node at (0,-2.9) {\LARGE Software};
        }

        \only<3->{
        \draw[color=red, ultra thick, fill=red, opacity=0.3] (-1.73,1) circle (3);
        \node at (-2.8,1.6) {\LARGE Hardware};
        }

        \only<4->{
        \node at (0,0) {\LARGE HPC};
        }
      \end{tikzpicture}}%>>>
  \end{columns}

\end{frame}
%>>>

% FUTURE PROOFING OUT METHODS AND CODES
% Domain Specific Languages ⇒ Domain Specific Architectures
%closely follow emerging hardware trends and plan for the future. arm, high bandwidth memory, accelerators

% Every tradesperson should know the tools of their trade.
% For HPC, those tools are your hardware and the programming language that you use.
% (we build abstract models of the hardware to keep things simple and this
% depends on the programming language view to some extent
% Von Neumann architecture)

\begin{frame} \frametitle{Trends in hardware}{} %<<<
  % Top 10 supercomputers
  % 3 have AMD Instinct GPU
  % 4 have NVIDIA GPU
  % 5 have AMD CPU
  % 2 have POWER9 CPU
  % 1 has Intel CPU
  % 1 has ARM CPU

  % exascale computing

  % heterogeneous computing, specialized hardware accelerators: GPUs, ASICS, FPGA, Tensor processing units
  % AMD GPUs becoming more common, Intel Xe GPU to feature in Aurora suprcomputer

  % energy efficiency

  % new memory technologies:
  % - Hybrid Memory Cube
  % - DDR6
  % - High Bandwidth Memory (HBM, HBM2, ...)

\end{frame}
%>>>

\begin{frame}[t] \frametitle{Trends in hardware}{} %<<<

  \begin{columns}
    \column{0.2\textwidth}
    \column{0.8\textwidth}
      %\write18{wget -O figs/trends0.png https://github.com/karlrupp/microprocessor-trend-data/raw/master/50yrs/50-years-processor-trend.png}
      %\write18{wget -O figs/trends1.png https://upload.wikimedia.org/wikipedia/commons/0/00/Moore\%27s_Law_Transistor_Count_1970-2020.png}
      \includegraphics[width=0.99\textwidth]{figs/trends0.png}
  \end{columns}

  % post Moore's law
  % Dennard scaling: end of frequency scaling
  % multi-core / many-core
  % vector lengths (512-bit now standard in most CPU cores)

  % rise of ARM (RISC ISA)

  % transistor counts increasing -- multi-package CPUs (NUMA) -- AMD Risen 64 cores

  %https://www.karlrupp.net/2018/02/42-years-of-microprocessor-trend-data/


\end{frame}
%>>>

\begin{frame} \frametitle{Trends in hardware}{} %<<<

  \begin{columns}
    \column{0.7\textwidth}
      \center
      \includegraphics[width=0.99\textwidth]{figs/sustained-memory-bw-falling-graph-mccalpin-1000x}

      {\scriptsize Source: John McCalpin - Memory bandwidth and system balance in HPC systems, 2016}

    \column{0.3\textwidth}
  \end{columns}


\end{frame}
%>>>

\begin{frame}[t] \frametitle{Trends in hardware}{} %<<<

  \vspace{-1.5em}
  \begin{columns}[t]
    \column{0.5\textwidth}
    \column{0.5\textwidth}
      \center
      \includegraphics[width=0.9\textwidth]{figs/Graphics-card-with-HBM-1}

      \includegraphics[width=0.6\textwidth]{figs/HBM}

      {\scriptsize Source: \url{https://www.amd.com/en/technologies/hbm}}
  \end{columns}

  % Intel recently announced that High-Bandwidth Memory (HBM) will be available on select “Sapphire Rapids” Xeon SP processors and will provide the CPU backbone for the “Aurora” exascale supercomputer to be sited at Argonne National Laboratory.
  %https://www.nextplatform.com/2021/10/21/how-high-bandwidth-memory-will-break-performance-bottlenecks/

\end{frame}
%>>>

\begin{frame} \frametitle{Trends in software}{} %<<<

  % programming languages: interpreted, JIT, code-generation,
  % - new languages (modern C++ - SCC sciware)
  % - features

  % Switch from interpreted to JIT (eg. MATLAB)

  % know how your programming language works
  % don't iterate over billion element array in python

  % compilers
  % compiler options for best performance

  % profilers and debuggers

  % optimized libraries for scientific computing: (BLAS, LAPACK, FFTW)
  % use whenever it makes sense to do so

  % HIP (NVIDIA and AMD GPUs)
  % HIP increasingly being instead of CUDA
  % hipify tool converts source from CUDA to HIP

\end{frame}
%>>>

\begin{frame} \frametitle{Programming languages}{} %<<<

  % programming languages: interpreted, JIT, code-generation,
  % - new languages (modern C++ - SCC sciware)
  % - features

  % Switch from interpreted to JIT (eg. MATLAB)

  % know how your programming language works
  % don't iterate over billion element array in python

  % compilers
  % compiler options for best performance

  % profilers and debuggers

  % optimized libraries for scientific computing: (BLAS, LAPACK, FFTW)
  % use whenever it makes sense to do so

  % HIP (NVIDIA and AMD GPUs)
  % HIP increasingly being instead of CUDA
  % hipify tool converts source from CUDA to HIP

\end{frame}
%>>>

%%%% \begin{frame} \frametitle{Resources}{} %<<<
%%%%   % SCC Sciware lectures
%%%% \end{frame}
%%%% %>>>